Memory sensing circuit

ABSTRACT

A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 12/125,866, filed on May 22, 2008, by Parviz Keshtbod, andentitled “Memory Sensing Circuit”, which is a continuation-in-part ofU.S. application Ser. No. 12/040,801 filed on Feb. 29, 2008, entitled“An Improved Low Resistance High-TMR Magnetic Tunnel Junction andProcess for Fabrication Thereof,” which is a continuation-in-part ofU.S. application Ser. No. 11/674,124 filed on Feb. 12, 2007, entitled“Non-Uniform Switching Based Non-Volatile Magnetic Based Memory,” whichclaims priority to U.S. Provisional Application No. 60/853,115 filed onOct. 20, 2006 entitled “Non-Uniform Switching Based Non-VolatileMagnetic Based Memory”; and is a further continuation-in-part of U.S.application Ser. No. 11/678,515 filed Feb. 23, 2007, entitled “A HighCapacity Low Cost Multi-State Magnetic Memory,” which claims priority toU.S. Provisional Application No. 60/777,012 filed Feb. 25, 2006 entitled“A High Capacity Low Cost Multi-State Magnetic Memory”; and is a furthercontinuation-in-part of U.S. application Ser. No. 11/739,648, filed Apr.24, 2007 entitled “Non-Volatile Magnetic Memory with Low SwitchingCurrent and High Thermal Stability”; and is a furthercontinuation-in-part of U.S. application Ser. No. 11/740,861, filed Apr.26, 2007, titled “High Capacity Low Cost Multi-Stacked Cross-LineMagnetic Memory”; and is a further continuation-in-part of U.S.application Ser. No. 11/776,692, filed Jul. 12, 2007, titled“Non-Volatile Magnetic Memory Element with Graded Layer”; and is afurther continuation-in-part of U.S. application Ser. No. 11/860,467filed Sep. 24, 2007, titled “Low cost multi-state magnetic memory”; andis a further continuation-in-part of U.S. application Ser. No.11/866,830 filed Oct. 3, 2007 entitled “Improved High Capacity Low CostMulti-State Magnetic Memory”; and is a further continuation-in-part ofU.S. application Ser. No. 11/932,940 filed Oct. 31, 2007 entitled“Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) forMagnetic Random Access Memory (MRAM),” which claims priority to U.S.Provisional Application No. 60/863,812 filed Nov. 1, 2006 entitled“Novel Spintronic Device.”

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to magnetic memory element andparticularly to sensing (or reading) of and writing to the magneticmemory element and an array made of the same.

2. Description of the Prior Art

Computers conventionally use rotating magnetic media, such as hard diskdrives (HDDs), for data storage. Though widely used and commonlyaccepted, such media suffer from a variety of deficiencies, such asaccess latency, the data not being randomly accessible, higher powerdissipation, large physical size and inability to withstand any physicalshock. Thus, there is a need for a new type of storage device devoid ofsuch drawbacks.

Other dominant storage devices are dynamic random access memory (DRAM)and static RAM (SRAM) which are volatile and very costly but have fastrandom read/write access time. Solid state storage, such assolid-state-nonvolatile-memory (SSNVM) devices having memory structuresmade of NOR/NAND-based Flash memory, providing fast access time,increased input/output (IOP) speed, decreased power dissipation andphysical size and increased reliability but at a higher cost which tendsto be generally multiple times higher than hard disk drives (HDDs).

Although NAND-based flash memory is more costly than HDD's, it hasreplaced magnetic hard drives in many applications such as digitalcameras, MP3-players, cell phones, and hand held multimedia devices due,at least in part, to its characteristic of being able to retain dataeven when power is disconnected. However, as memory dimensionrequirements are dictating decreased sizes, scalability is becoming anissue because the designs of NAND-based Flash memory and DRAM memory arebecoming difficult to scale with smaller dimensions. For example,NAND-based flash memory has issues related to capacitive coupling, fewelectrons/bit, poor error-rate performance and reduced reliability dueto decreased read-write endurance. Read-write endurance refers to thenumber of reading, writing and erase cycles before the memory starts todegrade in performance due primarily to the high voltages required inthe program, erase cycles. The flash-type non-volatile memories aretypically capable of writing one type of data randomly (e.g. 0's), towrite other types of data a larger section of the memory needs to beerased.

It is believed that NAND flash, especially multi-bit designs thereof,would be extremely difficult to scale below 45 nanometers. Likewise,DRAM has issues related to scaling of the trench capacitors leading tovery complex designs which are becoming increasingly difficult tomanufacture, leading to higher cost.

Currently, applications commonly employ combinations of EEPROM/NOR,NAND, HDD, and RAM as a part of the memory in a system design. Design ofdifferent memory technology in a product adds to design complexity, timeto market and increased costs. For example, in hand-held multi-mediaapplications incorporating various memory technologies, such as NANDFlash, DRAM and EEPROM/NOR flash memory, complexity of design isincreased as are manufacturing costs and time to market. Anotherdisadvantage is the increase in size of a device that incorporates allof these types of memories therein.

There has been an extensive effort in development of alternativetechnologies such as Ovanic Ram (or phase-change memory), FerromagneticRam (FeRAM), current Magnetic Ram (MRAM), Nanochip, and others toreplace memories used in current designs such as DRAM, SRAM, EEPROM/NORflash, NAND flash and HDD in one form or another. Although these variousmemory/storage technologies have created many challenges, such asrequiring too much current or having a large cell size or not readilyscalable, there have been advances made in this field in recent years.Current MRAM designs seem to lead the way in terms of its progress inthe past few years to replace all types of memories in the system as auniversal memory solution.

An MRAM element generally consists of a magnetic tunnel junction (MTJ)and an access transistor. A magnetic tunnel junction (MTJ) generallyconsists of a tunneling layer, such as one made of magnesium oxide (MgO)formed between two magnetic layers.

Electron current tunneling through the tunneling layer depends on theorientation of the two magnetic layers. If the magnetic orientations ofthe two magnetic layers are parallel, electrons have a relatively easytime tunneling through the tunneling layer, otherwise, tunneling isdifficult and some of the electrons are reflected at the interface.Therefore, the total resistance of the MTJ is less when the directionsof the magnetic orientation of the magnetic layers are parallel relativeto each other. If the resistance of the MTJ is Rl (or R_(low)) when themagnetic directions are parallel, and Rh (or R_(high)) when they areanti-parallel, the relative change of resistance is defined as(R_(h)−R_(l))/Rl, which is a measurement of tunneling magneticresistance (TMR). That is, the following equation defines TMR as:

TMR=(Rh−Rl)/Rl  Eq. (1)

The first time a product is manufactured, the magnetic orientations inall the MTJs are typically in the same direction, such as in a parallelstate. Therefore, the resistances of all the memory elements are atR_(l). After writing a “1” (or an active logic state, which may beconsidered “0” in certain cases), the resistance changes to R_(h). Dueto noise and other natural variances in the manufacturing process andwrite operations, the value of the resistances (R_(l) or R_(h)) form aGaussian distribution around certain R_(low) _(—) _(avg) and R_(high)_(—) _(avg). In reading a memory cell, which includes a memory element,its resistance is determined and based on its detected resistance, itslogical state is determined as being a “0” or “1”. To do so, the memorycell resistance is compared to a resistor with the average value ofRavg=(R_(low) _(—) _(avg) R_(high) _(—) _(avg))/2. When theR_(high)−R_(avg) is larger than a certain value V0 for a particularmemory cell, the cell is read as “1”, and when R_(avg)−R_(low) is largerthan V0 for a particular memory cell, the cell is read as “0”. If thevalues are less than V0, the memory cell state is undetermined and cannot be read. The V0 value is related to the sensitivity of the senseamplifier. For instance, the value of V0 is smaller for more sensitivesense amplifier.

However, one of the problems associated with the foregoing is that thevalue of the V0 can not be lowered indefinitely because of the presenceof thermal noise as well as noise generated by the switching of signalsfrom one state to another. This requires the value of V0 to be largerthan Vnoise by several orders of magnitude.

What is needed is a circuit for reliably sensing and writing to MRAMmemory cells.

SUMMARY OF THE INVENTION

To overcome the limitations in the prior art described above, and toovercome other limitations that will become apparent upon reading andunderstanding the present specification, the present invention disclosesa design method and a corresponding structure for a magnetic storagememory device that is based on spincurrent-induced-magnetization-switching having reduced switching currentin the magnetic memory.

Briefly, an embodiment of the present invention includes a sensingcircuit having a sense amplifier circuit having a first and second nodesthrough which a magnetic memory element is sensed. A first currentsource is coupled to the first node a second current source is coupledto the second node. A reference magnetic memory element has a resistanceassociated therewith and is coupled to the first node, the referencemagnetic memory element receives current from the first current source.At least one memory element, having a resistance associated therewith,is coupled to the second node and receives current from the secondcurrent source. Current from the first current source and current fromthe second current source are substantially the same. The logic state ofat least one memory element is sensed by a comparison of the resistanceof the at least one memory element to the resistance of the referencemagnetic memory element.

In another embodiment, a magnetic memory write circuit is disclosed toinclude a magnetic memory element coupled to a bit line on one end andan access transistor coupled to an opposite end of the magnetic memoryelement and operative to select the magnetic memory element to be reador written thereto. The access transistor is further coupled to a wordline, the magnetic memory element are selected to be read from orwritten to when the bit line and word line are activated. A firstinverter has an output coupled to the bit line and an input coupled toan input of the magnetic memory write circuit and a second inverter hasan input coupled to the input of the magnetic memory write circuit andfurther having an output and a third inverter has an input coupled tothe output of the second inverter and an output coupled to the source ofthe access transistor and to ground.

These and other objects and advantages of the present invention will nodoubt become apparent to those skilled in the art after having read thefollowing detailed description of the preferred embodiments illustratedin the several figures of the drawing.

IN THE DRAWINGS

FIG. 1 shows the structure of a reference magnetic memory element, inaccordance with an embodiment of the present invention.

FIG. 2 shows a sensing circuit, in accordance with an embodiment of thepresent invention.

FIG. 3 shows relevant details of the sense amplifier circuit 230, inaccordance with an embodiment of the present invention.

FIG. 4 shows a timing diagram of the nodes 54 and 56. The node 54generates the signal 99 and the node 56 generates the signal 91.

FIG. 5 shows a flow chart of the steps performed by the sense amplifier230 when sensing a memory element such as the memory element 100.

FIG. 6 shows a write circuit 102, in accordance with an embodiment ofthe present invention.

FIG. 7 shows a memory array 320 made of magnetic memory elements andincluding circuits for reading and writing to the same, in accordancewith an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following description of the embodiments, reference is made tothe accompanying drawings that form a part hereof, and in which is shownby way of illustration of the specific embodiments in which theinvention may be practiced. It is to be understood that otherembodiments may be utilized because structural changes may be madewithout departing from the scope of the present invention.

It is understood that as used herein “magnetic memory element”, “memoryelement”, “reference magnetic memory element” or “reference memoryelement”, or “magnetic random access memory (MRAM)” all refer tomagnetic memory that is made of MTJ. Various embodiments of thestructure used for a memory element are shown and discussed in thefollowing documents:

-   -   U.S. application Ser. No. 11/674,124, filed Feb. 12, 2007,        titled “Non-Uniform Switching Based Non-Volatile Magnetic Based        Memory” by Ranjan et alia,    -   U.S. application Ser. No. 11/678,515, Filed Feb. 23, 2007,        titled “A High Capacity Low Cost Multi-State Magnetic Memory” by        Ranjan et alia,    -   U.S. application Ser. No. 11/739,648 Filed Apr. 24, 2007, titled        “Non-volatile Magnetic Memory With Low Switching Current and        High Thermal Stability” by Ranjan et alia,    -   U.S. application Ser. No. 11/776,692, filed Jul. 12, 2007,        titled “Non-Volatile Magnetic Memory Element with Graded Layer”        by Ranjan et alia,    -   U.S. application Ser. No. 11/740,861, filed Apr. 26, 2007,        titled “High Capacity Low Cost Multi-Stacked Cross-Line Magnetic        Memory” by Ranjan et alia,    -   U.S. Application No. 60/863,812, filed Nov. 1, 2006, titled        “Novel Spintronic Device” by Wang,    -   U.S. application Ser. No. 11/932,940 filed Oct. 31, 2007 titled        “Current-Confined Effect Of Magnetic Nano-Current-Channel (NCC)        For Magnetic Random Access Memory (MRAM)” by Wang;    -   U.S. application Ser. No. 11/866,830 filed Oct. 3, 2007, titled        “Improved High Capacity Low Cost Multi-State Magnetic Memory” by        Ranjan et alia;    -   U.S. application Ser. No. 11/860,467 filed Sep. 24, 2007, titled        “Low cost multi-state magnetic memory” by Ranjan et alia; and    -   U.S. application Ser. No. 12/040,801, filed on Feb. 29, 2008,        titled “An Improved Low Resistance High-TMR Magnetic Tunnel        Junction and Process For Fabrication Thereof” by Ranjan, the        disclosures of which are incorporated herein by reference as        though set forth in full.

In various embodiments of the present invention, a reference magneticmemory element is used to read magnetic memory elements. The referencemagnetic memory element is similar to any one of the magnetic memoryelements being read or written and is therefore an MRAM element andideally has associated therewith a resistance value of R_(avg)=(R_(low)_(—) _(avg)+R_(high) _(—) _(avg))/2, which is then used to as areference resistance in reading the MRAM memory elements. As notedearlier, the MRAM memory elements each include an MTJ. However, sincethe exact shape of the MTJ resistance distribution when the memoryelements are first manufactured remains unknown, making a memory elementthat has a resistance value represented by:

R _(avg)=(R _(low) _(—) _(avg) +R _(high) _(—) _(avg))/2  Eq. (2)

is difficult. R_(avg) is the average resistance of the low resistancevalues R_(low) _(—) _(avg) and the average of the high resistance valuesR_(high) _(—) _(avg). Thus, in place of R_(avg), which represents moreof an exact average resistance value, a resistance value of R_(v) isused in accordance with the following relationship:

R _(v)=(R _(low) +R _(high))/2  Eq. (3)

R_(v) is obviously different from R_(avg) in that it is the average oflow and high resistance values rather than an average of the same,therefore, causing more difficulty in sensing (or reading of the memoryelements).

Referring now to FIG. 1, the structure of a reference magnetic memoryelement 10, in accordance with an embodiment of the present invention.The reference element 10 is shown to include MTJs 20, 22, 24 and 26 andhas a resistance value represented by R_(v) of Eq. (3), in accordancewith an embodiment of the present invention. The MTJs 20, 22, 24 and 26,initially each have a resistance value of R_(low). This is because thefirst time MRAM elements are manufactured, their resistances are set toR_(low).

MTJs 20 and 22 are coupled together in parallel and the MTJs 24 and 26are coupled together in parallel. The MTJ 20 is coupled, in series, withthe MTJ 24, at a node 16, and the MTJ 22 is coupled, in series, with theMTJ 26 at a node 14.

A formatting circuit 12 is shown coupled, at its output, to the MTJs 22and 26 at the node 14. The MTJs 20 and 22 are coupled to the formattingcircuit at its control gate. The formatting circuit 12 functions as anamplifier which pumps programming current through the MTJs 20 and 22,changing their resistance values to R_(high). The MTJs 24 and 26 areconnected at ends (or nodes) opposite to the nodes 16 and 14,respectively, to a source of an access transistor 18. The gate of theaccess transistor 18 is coupled to the word line 32 and the drain of theaccess transistor 18 is coupled to virtual ground. Virtual ground, asused herein, refers to a node that is maintained at a steady referencepotential (or voltage level) (during read operations) while fluctuatingbetween at least two states (or voltage levels) during write operations.The MTJs 20 and 22 are coupled at nodes opposite to the nodes 16 and 14,respectively, to a bit line 30.

In operation and before the memory elements are tested, a formattingoperation is performed by activating the formatting circuit 12, at itsinput thereby causing programming of the MTJ 20 and 22 under averageconditions, which results in increasing the resistance values of theMTJs 20 and 22 to R_(high). The collective resistance value of the MTJs20 and 22 is represented by the average of R_(low) and R_(high) or thefollowing equation:

R _(avg)=(R _(low) +R _(high))/2  Eq. (4)

Tunneling magnetic resistance (TMR) is defined as:

TMR=(R _(high) −R _(low))/R _(low)  Eq. (5)

Relative to TMR, the R_(high) is defined as:

R _(high) =R _(low)*(1+TMR)  Eq. (6)

and R_(avg) is defined as:

R _(avg) =R _(low)*(1+TMR/2)  Eq. (7)

During a read operation, the resistance values of the selected MTJwithin a memory array (or the MTJ that is selected to be read) iscompared to the average resistance formed by the MTJs 20, 22, 24 and 26.If the resistance value of the selected MTJ is higher than R_(avg), theresult is a logical state ‘1’, and if it is less than R_(avg) the resultis logical state ‘0’, or vice versa.

The average resistance, while perhaps not representing the exactaverage, as the average changes due to manufacturing and other factors,represents a resistance value that is close to an average of the highand low resistances. As the high and low resistances may not be absolutein and of themselves, with a variance associated with each, the averageresistance, using the method and apparatus of the embodiments of thepresent invention, is close enough to a middle range so as to avoidmis-write or mis-read.

As previously noted, a magnetic memory element includes an MTJ made of atunneling (or barrier) layer sandwiched between two magnetic layers. Oneof the magnetic layers is typically a free layer whose magneticorientation transitions from one that is parallel to that of the othermagnetic layer (known as the fixed layer) to one that is anti-parallelto that of the fixed layer. The thickness of the tunneling layer and thephysical size of the memory element, upon which TMR is based, generallydetermine the resistance values to which the resistors 20-26 should beset. This is evidenced by the equations above. As an example, where thethickness of the tunneling layer is 10 to 15 A and the physical size ofthe memory element is 0.1 to 0.2 u2, a R_(high) resistance value is 1400ohms and a R_(low) resistance value is 600 ohms with an averageresistance of 1000 ohms. Therefore, the resistance of a magnetic memoryelement that is to be read is compared to 1000 ohms and if it is higher,for example, the memory element may be declared as being at a high logicstate and if it is lower than 1000 ohms, the memory element may bedeclared as being at a low logic state. Thus, rather than simply using areference voltage to compare to in determining the logical state of amemory element, as done by prior art techniques, in one embodiment ofthe present invention, the average value of the resistance of two MTJsare used to compare to the resistance of the MTJ (or memory element)being read.

FIG. 2 shows a magnetic memory sensing circuit 40 for sensing (orreading) the state of a magnetic memory element 100, which is made of aMTJ or the state of the magnetic memory element 240, which is also madeof a MTJ, using the reference memory element 10, in accordance with anembodiment of the present invention. As used herein, a memory elementincludes a MTJ and a memory cell includes a memory element and acorresponding access (or select) transistor.

Memory element 100 and memory element 240 may be each made of any of thememory elements shown and discussed in the following patent document:

-   -   memory element are shown and discussed in the following        documents:    -   U.S. application Ser. No. 11/674,124, filed Feb. 12, 2007,        titled “Non-Uniform Switching Based Non-Volatile Magnetic Based        Memory” by Ranjan et alia,    -   U.S. application Ser. No. 11/678,515, Filed Feb. 23, 2007,        titled “A High Capacity Low Cost Multi-State Magnetic Memory” by        Ranjan et alia,    -   U.S. application Ser. No. 11/739,648 Filed Apr. 24, 2007, titled        “Non-volatile Magnetic Memory With Low Switching Current and        High Thermal Stability” by Ranjan et alia,    -   U.S. application Ser. No. 11/776,692, filed Jul. 12, 2007,        titled “Non-Volatile Magnetic Memory Element with Graded Layer”        by Ranjan et alia,    -   U.S. application Ser. No. 11/740,861, filed Apr. 26, 2007,        titled “High Capacity Low Cost Multi-Stacked Cross-Line Magnetic        Memory” by Ranjan et alia,    -   U.S. Application No. 60/863,812, filed Nov. 1, 2006, titled        “Novel Spintronic Device” by Wang,    -   U.S. application Ser. No. 11/932,940 filed Oct. 31, 2007 titled        “Current-Confined Effect Of Magnetic Nano-Current-Channel (NCC)        For Magnetic Random Access Memory (MRAM)” by Wang;    -   U.S. application Ser. No. 11/866,830 filed Oct. 3, 2007, titled        “Improved High Capacity Low Cost Multi-State Magnetic Memory” by        Ranjan et alia;    -   U.S. application Ser. No. 11/860,467 filed Sep. 24, 2007, titled        “Low cost multi-state magnetic memory” by Ranjan et alia; and    -   U.S. application Ser. No. 12/040,801, filed on Feb. 29, 2008,        titled “An Improved Low Resistance High-TMR Magnetic Tunnel        Junction and Process For Fabrication Thereof” by Ranjan.

In FIG. 2, the sensing circuit 40 is shown to include a sense amplifiercircuit 230 coupled to a decoding transistor 214 and further coupled toa decoding transistor 216, at their source. The drain of the transistor214 is shown coupled to the reference memory element (MTJ) 10 and servesas a reference bit line. The reference memory element 218 is furthershown coupled to a transistor 242 at the drain of the transistor 242.The gate of the transistor 242 forms a reference word line 220 and thesource of the transistor 242 forms the virtual ground (Ver) 238, whichis shown coupled to the source of the transistor 222.

The drain of the transistor 222 is shown coupled to the memory element100 and an opposite end of the memory element 100 is shown coupled tothe drain of the transistor 216 forming the bit line 1 244. The sourceof the transistor 222 is shown coupled to the source of the transistor224 and to the source of the transistor 242 forming Ver 238. The gate ofthe transistor 224 is shown to form the word line 2 228. The drain ofthe transistor 224 is shown coupled to the memory element 240, which onan opposite end thereto, forms the bit line 2 246.

Ver 238 is shown coupled to the drain of the transistor 51, which hasits gate coupled to the same, i.e. Ver 238. The source of the transistor51 is shown coupled to the drain of the transistor 53, which has itssource coupled to (actual) ground. The gate of the transistor 53 iscoupled to the read enable signal 324, which serves to initiate a readoperation. The gate of the transistor 53, 60 goes high during readoperation and is grounded during write operation of the selected MTJ.

The gate of transistor 216 is coupled to an address decoder (not shown).In some embodiments, the transistor 216 is part of an address decoder,which selects which memory element is to be read or written thereto. Inthe embodiment of FIG. 2, the transistor 216 might select the memoryelement 100 while another transistor of the address might select thememory element 240. The gate of the transistor 214 is shown coupled toVcc (or a high state). The transistors 52, 54, 216, 214, 222, 221 and242 are each of the NMOS type of transistors

Transistors 42, 44 and 46 are shown coupled in parallel relative to eachother with the drains thereof being coupled to high voltage defining apower supply (or Vcc). The drains of transistors 42 and 44 are eachshown coupled to either sides of the sense amplifier 230. That is, thedrain of the transistor 42 is shown coupled between the sense amplifier230 and the drain of the transistor 214 at reference magnetic memoryelement sensing node 50 and the drain of the transistor 44 is showncoupled between the sense amplifier and the source of the transistor 216at magnetic memory element sensing node 52. The drain of the transistor46 is shown coupled to the resistor 55, which on an apposite endthereof, is shown coupled to (actual) ground.

The sense amplifier 230 senses potential or voltage levels at the nodes50 and 52 and compares them to determine which has a higher potentialwhich is related to the higher resistance of the MTJs. This is donebecause of the well-known relationship between voltage (V) beingresistance (R) multiplied by current (I). If the voltage at 52 isdetermined to be higher than that of the voltage at 50, the resistanceof the memory element 100 is then known to be higher than that of thememory element 10, thus, declaring the memory element 100 to be at highstate. Otherwise, if the voltage at node 52 is determined to be lowerthan that at node 50, the memory element 100 is determined to be at lowstate. It is understood that the opposite may be implemented in that thevoltage at node 52 being higher than that of node 50 yielding a lowstate and the voltage at node 52 being lower than that of the mode 50yielding a high state.

The transistors 42 and 44 and 46 function as current sources, providingsubstantially the same amount of current through the reference memoryelement 10 and each of the memory elements 100 and 240. That is, thecurrent generated by the current source (or transistor 42) to the memoryelement 100 or the memory element 240 is substantially identical, inamount, to the current generated by the current source (or transistor)42 to the memory element 10. The current source 43 is shown made of thetransistors 42, 44 and 46 and their connections to each other.

In one embodiment of the present invention, the logical state of each ofthe memory elements 100 and 240 is easily measured by comparing theresistance of each to that of the reference memory element 10. This isdone because the resistance of the reference memory element 10 is known,as previously discussed, and being that the current supplied to thereference memory element 10 and each of the memory elements is the same,the resistance of the latter is determined relative to the former. Forexample, if the resistance of the memory element 100 is determined to behigher than that of the reference memory element 10, the logic state ofthe memory element 100 may be determined as being ‘high’ or ‘1’,whereas, if the resistance of the memory element 100 is determined to belower than that of the reference memory element 10, the logic state ofthe memory element 100 may be determined as being ‘low’ or ‘0’,alternatively, the reverse of these states may be determined. It isunderstood that while two memory elements 100 and 240 are shown in FIG.2, any number of memory elements may be employed and their states readin accordance with the foregoing.

The transistors 51 and 53 are formed between the memory elements andactual ground because the amount of voltage generated due to the currentflowing through the MTJ is very low. This is because the currentsgenerated by the current sources are substantially approximately in themicro amperes range. Since the resistance of the MTJs is approximatelyin the kilo ohms range, the voltage generated across the MTJs is in themilli-volts range. The threshold of the sensing elements in the senseamplifier is larger than this. The transistor 51 is employed to bias thevoltage to a larger value in order to activate the transistor in thesense amp. The threshold of the transistor 51 is Vt, so that the voltageat the gate of the sensing element being read is Vt+V0, with V0 beingthe voltage generated by the MTJ resistor.

The function of the transistor 46 and the resistor 55 is to set thecurrent value for the current sources 42 and 44. That is, the resistancevalue of the resistor 55 determines the amount of current to be suppliedby each the current sources 42 and 44. Ideally, an identical amount ofcurrent is supplied by each of the current sources 42 and 44 to thememory element 10 and the memory elements to be read (or sensed).

During a read (or sensing) operation, the sense amplifier circuit 230compares the resistance of the memory element 100 (of the selected cell)to the resistance of the reference memory element 10. The resistance ofthe cell 10 is designed to be (R1+R2)/2, where R1 is the resistance ofthe memory element 100 in a low state and R2 is the resistance of thememory element 100 in high state. The high and low states are based onthe description provided above where the low state has a characteristicof being at least half of the resistance of that of the high state. Themagnetic orientation of the fixed and the free layers, i.e. the twomagnetic layers of the MTJ of the memory cell being read, are parallelrelative to each other at a low state and at a high state, the magneticorientation of the fixed and free layers are anti-parallel relative toeach other.

In one embodiment of the present invention, the sense amplifier 230 is abi-stable latch or any such device, which flips between logic statesbased on the state of the resistance. For example, if resistance is low,the state will be that of a low state and if resistance is high, thestate will be that of a high state.

It should be noted that the magnetic memory elements 100 and 240 are twoof many magnetic memory elements coupled to bit line 244. Thetransistors 222 and 224 are used to select one of these magnetic memoryelements based on the selection of one of the word lines 226 or 228.When a word line is selected, it is biased with the appropriatepotential required to turn on the selected transistors. When one of thetransistors 222 or 224 is selected, the memory element 100 is caused tobe coupled to the circuit 230, at 231, through the transistor 216, whichas a decoder circuit. At the same time the reference memory element 10is selected by the transistor 242 and the word line 220. Thereafter,current flows through the selected transistors, i.e. transistor 222 or224. The current flowing through the reference memory element 10 isalways the same, while current flowing through the selected memoryelements, such as the memory element 100 depends on the state of thatmemory element. That is, if the memory element's state is high, itsassociated resistance (R) is high with respect to the reference memoryelements. Thereafter, less current flows through the selected memoryelements than the reference memory element 218, causing the senseamplifier circuit 230, at 233, to enter a high state with respect tothat of 233. On the other hand, if the selected memory element is at alow state and has low resistance, its current is high with respect tothat of the reference memory element 218 and the voltage at 231 drops.In this manner, the voltage at 231 determines the state of the selectedmemory element.

The current provided by the current source 43 is at least, in part,controlled by the resistance value of the resistor 50. Programming orwriting of the memory cells 240 or 100 is also done by forcing highcurrent through the magnetic memory cells being read, however, the readcurrent can not be too high. High read currents can cause undesirableprogramming of the memory cells (or memory elements), which is commonlyreferred to as “read disturbance”. Therefore, the read current needs tobe below a certain critical current. This critical current depends onthe MTJ size. In an exemplary embodiment, the read current is less than40 uA (micro amps).

As currents flows through the memory cell and the reference memory cell,certain amount of voltage appears at the two ends of the sense amplifiercircuit 230. If the MTJ is programmed to a high resistance value(R_(high)), the voltage on the MTJ side of the sense amplifier 230, suchas the voltage of the memory cell 100, is higher than the voltage of theother side of the sense amplifier, such as the side with the referencememory element 10, by the following difference voltage (DV):

DV=Iread*(R _(high) −R _(avg))=Iread*R _(low)*TMR/2  Eq. (8)

If the memory element being read is programmed to a low logical state,such as ‘0’, the voltage on of the sense amplifier circuit 230 side thathas the memory element being read, such as the side having the memoryelement 100 is lower by:

DV=Iread*(R _(low) −R _(avg))=Iread*R _(low)*TMR/2  Eq. (9)

The typical values for TMR, Iread and R_(low) are 1, 40 uA and 1 KiloOhms, respectively. Therefore a typical DV is approximately 20 milliVolts (mV). As earlier indicated, the resistance values of the MTJ in amemory product are not the same all the time, partly due to varyingconditions under which such products are manufactured. For example, thethickness of the tunneling layer as well as the size of the memoryelement would vary the characteristics of the memory elements.

Thus, the resistance values of the MTJ in a memory product generallyfollow a Gaussian distribution with highs and lows. This effectivelyreduces the DV in reading of different cells under different conditions.Therefore, the product requires a sensitive sense amplifier circuit,such as the sense amplifier 230. A sensitive amplifier circuit however,can undesirably amplify noise and disturbances of the circuit. Toovercome this problem, sensing is slightly delayed, allowing undesirabledisturbances caused by switching of signals to subside.

FIG. 3 shows relevant details of the sense amplifier circuit 230, inaccordance with an embodiment of the present invention. The senseamplifier 230 is shown coupled to the current sources 42 and 44 and tothe reference memory element 10 and the memory element 100. It isunderstood that more memory elements may be coupled to the senseamplifier 230 than that shown in FIG. 3.

The sense amplifier 230 is shown to include transistors 88, 60, 82, 66,64, 84, 62 and 86 and the criss-cross latch 58 and the amplifiercircuits 68, 70 and 72. The criss-cross latch 58 is shown to includetransistors 74, 76, 78 and 80 and the amplifier circuit 68 is shown toinclude transistors 90, 92, 94 and 96. Criss-cross latch 58 is wellknown as are the amplifiers 68, 70 and 72. However, to overcome theproblem of undesirable amplification of noise and disturbances caused bythe switching of signals associated with the criss-cross latch 58, thesense amplifier 230 advantageously slightly delays sensing of thevoltages of the reference memory element and the memory element to beread to allow for the disturbances to subside before beginning sensing.

The transistors 74, 78, 90, 94, 46 and 66 are generally p-typetransistors and the transistors 92, 96, 86, 62, 84, 80, 76, 82 and 60are generally n-type transistors. In FIG. 3, the gate of the transistor88 is shown coupled to the source of the transistor 60. The source anddrain of the transistor 88 are shown coupled to actual ground The A node56 is shown coupled to the drain of the transistor 82 and the drain ofthe transistor 60 is shown coupled to ground. The node 52 is furthershown coupled to the drain of the transistor 76 and to the source of thetransistor 74. The drain of the transistor 60 are shown coupled toground. The source of the transistor 60 is shown coupled to the drain ofthe transistor 82. The source of the transistor 82 is shown coupled tothe node 52 and its gate is shown coupled to a Sab node 56. The sourceof the transistor 66 is shown coupled to the node 52, and its drain isshown coupled to the node 50 and its gate is shown coupled to a node Sae54. The gate of the transistor 64 is shown coupled to the node 54 andits drain is shown coupled to actual ground and its source is showncoupled to the respective sources of each of the transistors 80 and 76.The source of the transistor 84 is shown coupled to the node 50, itsdrain is shown coupled to the source of the transistor 62 and its gateis shown coupled to the node 56. The source and drains of the transistor86 are shown coupled to actual ground and its gate is shown coupled tothe drain of the transistor 84.

The drain of the transistor 74 is shown coupled to VCC and its source isshown coupled to the node 52 and its gate is shown coupled to the nodeand the source of the transistor 78. The source of the transistor 76 isshown coupled to the node 52 and the gate of the transistor 76 is showncoupled to the gate of the transistor 74 and the drain of the transistor76 is shown coupled to the source of the transistor 64. The gate of thetransistor 80 is shown coupled to the node 52, its drain is showncoupled to the node 50, its source is shown coupled to the source of thetransistor 64. The source of the transistor 78 is shown coupled to Vcc,its gate is shown coupled to the node 52 and to the gate of thetransistor 80 and its drain is shown coupled to the node 50. The gate ofthe transistor 74 is shown coupled to the node 50, its drain is showncoupled to the node 52 and its source is shown coupled to Vcc.

While the transistors 46, 42 and 44 are shown to be P-type transistorsin FIG. 3, they may be of N type, in alternative embodiments. In fact,any type of CMOS or bipolar transistor may be used as these transistors.Alternatively, another type of current source may be employed. It ishowever desirable to have the current provided by each of thetransistors 42 and 44 be substantially equal. In one embodiment of thepresent invention, the current produced by each one differs by 10% fromthe other one

The drain of the transistor 90 is shown coupled to Vcc, its source isshown coupled to the input of the amplifier 70 and its gate is showncoupled to the input of the amplifier 72. The drain of the transistor 94is shown coupled to the Vcc and its gate is shown coupled to the inputof the amplifier 70 and its source is shown coupled to the amplifier 72.The drain of the transistor 92 is shown coupled to the input of theamplifier 70, its gate is shown coupled to the node 52 and its source isshown coupled to ground. The drain of the transistor 96 is shown coupledto the input of the amplifier 72, its gate is shown coupled to the node50 and its source is shown coupled to ground.

The amplifier 68 amplifies the output of the criss-cross latch 58 andone of the amplifiers 70 or 72 acts to further amply the output of thecriss-cross latch 58. Use of both amplifiers helps to balance the twosides of the criss-cross latch 58 although in alternative embodiments, asingle amplifier may be employed. Additionally, the amplifiers 68, 70and 72 may be one amplifier in other embodiments. It is understood thatother combinations of amplifiers may be employed.

In operation, during sensing or reading of a memory element, such as thememory element 100, the latter is advantageously sense not immediately,rather a delay is introduced prior to the time the sense amplifier 230starts reading. Namely, the address of the memory element to be read isnot latched (or captured) until some time after the reading operationstarts. This is done by delaying activation of the sense amplifier 230.The delay is a design choice an in an exemplary embodiment is in theorder of a couple of nano seconds.

In an exemplary embodiment, upon selection of the memory element 100 bythe decoder 216 through the bit line 244, after a predetermined delay,the sense amplifier 230 is activated by raising the voltage at each ofthe nodes Sab 56 and Sae node 54. The Sae node 54, when activated,causes the activation of the criss-cross latch 58, which stays activatedduring the remainder of the read operation. Activation of the Sab node56 causes coupling of the criss-cross latch 58 to the transistors 60 and62. As earlier indicated, the node 56 is activated for a short period oftime, such as a couple of nano seconds. While the node 56 is high (oractivated), the two transistors 60 and 62 pull on the different sides ofthe criss-cross latch 58. That is, the transistor 60 pulls the node 52and the transistor 62 pulls the node 50. The node with the highervoltage pulls its side of the criss-cross latch 58 toward ground. Thismakes the criss-cross latch 58 unbalanced with each of the nodes 50 and52 being at voltage levels different than one another, in fact, when onenode raises in potential by a certain amount, the other node lowers inpotential by substantially the same certain amount. This trend continueseven after the node 56 is deactivated, and one side of the criss-crosslatch 58 eventually is driven to ground, indicating the memory elementwith the higher potential and therefore higher resistance. Accordingly,the potential of each of the nodes 52 and 50 is compared by thecriss-cross latch 58 and the result is amplified by amplifiers andultimately latched. For example, the amplifiers 68 and 72 amplify thesignals to solid 0s and 1s.

In summary, in an exemplary embodiment, a memory element and a referencememory element are selected through a decoder. The current sources toeach are also activated. The voltages generated by the currents flowingthrough the memory element and the reference memory element are appliedto the gates of the transistors 60 and 62, respectively.

FIG. 4 shows a timing diagram of the nodes 54 and 56. The node 54generates the signal 99 and the node 56 generates the signal 91. Anenable signal, chip enable (CEB) 95 activates a chip or device includingan array of memory elements having MTJs, such as the memory elements 100and 240. Address signals 97 carry the address of the memory element tobe sensed.

In one embodiment of the present invention, the decoder transistors 216and 214 are a part of the address logic that are selected by the address97 although it is understood that these transistors are two among manyothers.

After the selection of a memory element by activation of the signal 95and the indicated address on the address signals 97 the desired memoryelement is selected, the sense amplifier 230 is activated by raising thevoltages at the node 54 followed by raising the voltage at the node 56for a short time. In an exemplary embodiment, the node 56 is raised oractivated 5 nano seconds after activation of the node 54. Activation ofthe node 56 causes coupling the criss-cross latch 58 of the senseamplifier 230 to the transistors 60 and 62. The node 56 remainsactivated only for a short time, such as a couple of nano seconds,during which time, the two transistors 60 and 62 pull on the differentsides of the criss-cross latch 58 to start the latching process. Thecriss-cross latch 58 is also known as a “cross-coupled latch”.

FIG. 5 shows a flow chart of the steps performed by the sense amplifier230 when sensing a memory element such as the memory element 100. Atstep 300, the node 54 is enabled (or activated) and then a predeterminedperiod of time is awaited at 302 and 304, an example of such time is 5nano seconds. Then the node 56 is enabled. This initiates the directionof the criss-cross latch 58 from the balanced position, i.e. thevoltages at each of its sides are off with respect to each other. Next,at step 310, the node 56 is deactivated after which the output of thecriss-cross latch 58 is amplified at step 312 and thereafter, the node54 is disabled and the address of the memory element to be read islatched (or captured or stored).

The time period from enabling the node 56 at step 306 to deactivating itat step 310 is fairly short. This initiates the movements of two sidesof the criss-cross latch. When the movements start, they will continueautonomously. FIG. 6 shows a magnetic memory write circuit 102, inaccordance with an embodiment of the present invention. The writecircuit 102 is a circuit for writing to the magnetic memory element 104,made of a MTJ and is shown to include the memory element 104, an accesstransistor 106 and the invertors 110-114. Data to the memory element 104is written at the node 116, in accordance with a method and apparatus ofthe present invention.

The access transistor 106 is shown to be coupled to the word line 118 atits gate and to virtual ground 108 at its source and to one side of thememory element 104 at its drain. At an opposite side thereof, the memoryelement 104 is shown coupled to the bit line 120. The memory element 104and the access transistor 106 collectively comprise a magnetic memorycell. The inverter 114 is shown to receive data at node 116 at itsinput, which is also coupled to the input of the inverter 112. Theoutput of the inverter 114 is shown coupled to the bit line 120 and theoutput of the inverter 112 is shown coupled to the input of the inverter110. The output of the inventor 110 is shown coupled to ground 108 andthe source of the transistor 106.

Virtual ground 108 fluctuates between states (or voltage levels groundand Vcc) depending on the logical state being written. That is, it isdriven, for example, to a logical state ‘1’, in the case where logicalstate ‘1’ is being written (or programmed) and it is driven to a state‘0’, in the case where logical state ‘0’ is being written. Similarly,bit line 120 is driven to a different voltage level, dictating aparticular logical state, depending on the logical state beingprogrammed. For example, when programming logical state ‘1’, bit line120 is driven to logical state ‘0’, in the embodiment of FIG. 6, andwhen programming logical state ‘0’, bit line 120 is driven to logicalstate ‘1’.

The high resistance of the memory element 104 is represented by anactive or high logic state “1” and is indicative of the two magneticlayers of its MTJ being in opposite orientation relative to each other.If the two magnetic layers have the same orientation, then theresistance of the memory element 104 is low and this is represented byan inactive or logical state “0”. Originally all memory elements are inthe “0” state (their two magnetic layers have magnetic moments inparallel). To have the memory element 104 take on a logical state, whichis commonly referred to as writing to the memory element, which is, forexample a “1” or high logical state, current need be forced to flow fromthe lower magnetic layer (or fixed layer) of the MTJ toward the topmagnetic layer, or the free layer. A state of “1” appears as the data tobe written at node 116. Conversely to write “0” current need be forcedfrom the top magnetic layer (free layer) of the memory element 104's MTJtoward its lower magnetic layer (fixed layer).

The write circuit 102 accomplishes the foregoing writing in thefollowing manner. When data, as “1”, appears at node 116, the output ofthe inventor 112 is “0” and the output of inverter 110 is “1”,therefore, virtual ground 108 is at a high or active or “1” state. Inthe meanwhile, the output of the inverter 114 is “0”, thus, the bit line120 is “0” thereby forcing current from the lower magnetic layer of thememory element 104 to its top magnetic layer. When the data at node 116is “0” or the memory element 104 is to be programmed or written to aninactive state, the reverse occurs and the output of the inverter 112 is“1” causing the output of the inverter 110 or the ground 108 to be “0”.In the meanwhile, the output of the inverter 114 is “1” and thereforethe bit line 120 is “1” thereby forcing current to flow from the topmagnetic layer of the memory element 104 to its lower magnetic layer.

It is understood that the inverters 110-114 can be replaced with anysuitable circuit or structure accomplishing an inversion function.

FIG. 7 shows a memory array 320 made of magnetic memory elements andincluding circuits for reading and writing to the same, in accordancewith an embodiment of the present invention. It is understood that thememory element 320 represents a portion of a potentially larger memoryarray made of additional memory elements. In one embodiment, the array320 is 4 kilobytes by 16 bits. Furthermore, memory arrays, stacked ontop of each other, with each stack including one of more of the memoryarray 320 are contemplated. Such memory arrays may formthree-dimensional arrays.

In FIG. 7, ‘n’ number of columns (or bit lines) and ‘m’ number of rows(or word lines) are shown coupled to magnetic memory arrays with ‘n’ and‘m’ being integer values. Magnetic memory elements are represented by aresistor symbol to indicate the resistive behavior thereof. It isunderstood that magnetic memory elements discussed herein behave likevariable resistors with their resistances changing depending upon theorientation of the two magnetic layers of the MTJ thereof. Theorientation of the free layer is set by the direction of the writecurrent flowing through the magnetic memory. Each magnetic memoryelement is shown coupled to its corresponding access transistor, whichserves to select the memory element. For example, the magnetic memoryelement 356, which is analogous to the memory element 100, is showncoupled to access transistor 358, which is analogous to the transistor222. The access transistor 358 serves to select the memory element 356.A column decoder 400 is shown coupled to a group of bit line selecttransistors (or decoders) 360, which in this case is ‘n’ number oftransistors. In an exemplary embodiment, the group of transistors 360includes the transistors 214 and 216. Each of the transistors of thegroup of transistors 360 serves to select or activate the bit line towhich it is coupled when it is activated by the column decoder 400. Theinput of the column decoder 400 is a part of the memory address providedto the array 320 to select a particular memory element to be written orread. The remainder of the address is provided to the row decoder 402,which selects one of the ‘m’ number of word lines. The part of theaddress that is coupled to the column decoder and includes a writeenable indicative of the start of a write operation is referred to as‘write enable/address 404.

As earlier noted, the row decoder 402 receives the remainder of theaddress to the array 320 and based thereupon, activates a word lineamong the ‘m’ number of word lines. The activation of a particular wordline and a particular bit line serve to select a memory element withinthe array 320 to be written to or read. The column decoder 400 and therow decoder 402 collectively decode the received address, accordinglyactivating a particular word line and bit line and thereby selecting amagnetic memory element to be written to or read.

Ver or virtual ground is shown coupled between the source of an accesstransistor of a word line to the drain of an access transistor of asubsequent word line.

A read enable signal 324 initiates a read (or sensing) operation, whichis performed as discussed herein using a reference magnetic memoryelement, as shown in FIG. 1. The data to be written during a writeoperation is introduced at node 322 and the write operation takes placeas discussed herein with reference to FIG. 6. It is understood that thewrite circuitry and read circuitry, as shown and discussed herein aresimplified in that in an actual design, provisions are made so that thewrite and read operation do not interfere with each other, as well knownto those skilled in the art. Thus, the inverters 338, 340 and 336 areanalogous to the inverters of FIG. 6.

In operation, to write to, for example, the memory element 356 currentflows in the direction indicated by the arrows starting from the memoryelement 356, flowing through the transistor 358, through Ver, and backup to the transistor 354 because the word line 332 are active to choosethe memory element 356, as would the column 328 be active. The currentflows through the transistor 354 back down to Ver and all the way downto the transistor 52 and to the transistor 54.

It is contemplated that the various embodiments of the presentinvention, such as those of FIGS. 1-7, have a variety of applications.For example, they may be used to replace hard disk drives as storagealthough, currently the costs may not justify such a substitute but inthe future, as costs of memory elements such as those of the presentinvention decrease, it is anticipated that such a replacement will bepractical. Alternatively, they may replace DRAM or other types ofdynamic and even static memory and/or other types of memory currently inuse. Another application of the various embodiments of the presentinvention includes the replacement of flash with the advantage that, forexample, the memory elements of the embodiments of the present inventioncan withstand far more programming/writing thereto than the life spanexperienced by flash cells. The scalability of the embodiments of thepresent invention allow the same to replace many types of memory orstorage devices.

Although the present invention has been described in terms of specificembodiments, it is anticipated that alterations and modificationsthereof will no doubt become apparent to those skilled in the art. It istherefore intended that the following claims be interpreted as coveringall such alterations and modification as fall within the true spirit andscope of the invention.

What is claimed is:
 1. A method of formatting a reference magnetic memory element employed in reading a magnetic memory element of an array of magnetic memory comprising: setting the resistance of a first, second, third and fourth magnetic tunnel junction (MTJ) of a reference magnetic memory element to Rlow, said second MTJ coupled in parallel to the first MTJ and said fourth MTJ coupled in parallel to the first MTJ, said first and third MTJs coupled together in series and said second and fourth MTJs coupled together in series; pumping programming current through the first and second MTJs thereby changing their resistance values to R_(high); and activating the formatting circuit causes programming of the first and second MTJs thereby increasing the resistance values of the first and second MTJs to R_(high), the collective resistance value of the first and second MTJs being represented by the average of R_(low) and R_(high).
 2. A method of sensing the state of a magnetic memory array comprising: generating current from a first current source; generating current from a second current source; receiving the first current source by a reference magnetic memory element; receiving the second current source by a magnetic memory element to be read; enabling a criss-cross latch that senses the voltage of a reference magnetic memory element and the voltage of a magnetic memory element to be read; waiting a first predetermined period of time to initiate placing the criss-cross latch in a particular direction; enabling initiation of placing the criss-cross latch in a particular direction; waiting a second predetermined period of time; deactivating the initiation; and amplifying and latching the state of the magnetic memory array. 